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november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series tisp4165h4bj thru tisp4200h4bj, tisp4265h4bj thru tisp4350h4bj high holding current bidirectional thyristor overvoltage protectors t r sd4xaa terminals t and r correspond to the alternative line designators of a and b device symbol device v drm v v (bo) v 4165 135 165 4180 145 180 4200 155 200 4265 200 265 4300 230 300 4350 275 350 waveshape standard i tsp a 2/10 s gr-1089-core 500 8/20 s iec 61000-4-5 300 10/160 s fcc part 68 250 10/700 s itu-t k.20/21 200 10/560 s fcc part 68 160 10/1000 s gr-1089-core 100 rated for international surge wave shapes 12 t(a) r(b) mdxxbg how to order smbj package (top view) description these devices are designed to limit overvoltages on the telephone line. overvoltages are normally caused by a.c. power system o r lightning flash disturbances which are induced or conducted on to the telephone line. a single device provides 2-point protection and is typically used for the protection of 2-wire telecommunication equipment (e.g., between the ring and tip wires for telephones and modems). comb inations of devices can be used for multi-point protection (e.g., 3-point protection between ring, tip and ground). the protector consists of a symmetrical voltage-triggered bidirectional thyristor. overvoltages are initially clipped by breakd own clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. this low-voltage on s tate causes the current resulting from the overvoltage to be safely diverted through the device. the high crowbar holding current prevents d.c. latchup as the diverted current subsides. itu-t k.20/21 rating ....................... 8 kv 10/700, 200 a 5/310 high holding current ........................................... 225 ma min. ion-implanted breakdown region precise and stable voltage low voltage overshoot under surge low differential capacitance ................................. 67 pf max. .............................................. ul recognized component *rohs directive 2002/95/ec jan 27 2003 including annex device package carrier TISP4XXXH4BJ bj (j-bend do-214aa/smb) embossed tape reeled TISP4XXXH4BJr bulk pack TISP4XXXH4BJ TISP4XXXH4BJr-s TISP4XXXH4BJ-s insert xxx value corresponding to protection voltages of 165 through to 350. for standard termination finish order as for lead free termination finish order as *r o h s c o m p l i a n t v e r s i o n s a v a i l a b l e
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series rati ng symbol value unit repe titive peak off-state voltage, (see note 1) 4165 4180 4200 4265 4300 4350 v drm 135 145 155 200 230 275 v non-repetitive peak on-state pulse current (see notes 2, 3 and 4) i tsp a 2/10 s( gr -1089-core, 2/10 s voltage wave shape) 500 8/20 s( iec 61000-4-5, 1.2/50 s voltage, 8/20 current combination wave generator) 300 10/160 s( fcc part 68, 10/160 s vo lt ag e wa ve shape) 250 5/200 s( v de 0433, 10/700 s voltage wave shape) 220 0.2/310 s (i3124, 0.5/700 s voltage wave shape) 200 5/310 s( itu-t k .20/21, 10/700 s voltage wave shape) 200 5/310 s( f tz r12, 10/700 s voltage wave shape) 200 10/560 s( fcc part 68, 10/560 s vo lt ag e wa ve shape) 160 10/1000 s( gr -1089-core, 10/1000 s voltage wave shape) 100 non-repetitive peak on-state current (see notes 2, 3 and 5) i tsm 55 60 2.1 a 20 ms (50 hz) full sine wave 16.7 ms (60 hz) full sine wave 1000 s 50 hz/60 hz a.c. initial rate of rise of on-state current, exponential current ramp, maximum ramp value < 200 a di t /dt 400 a/ s j unction temperature t j -40 to +150 c st or age temperature range t stg -65 to +150 c notes: 1. see applications information and figure 10 for voltage values at lower temperatures. 2. init ially, the TISP4XXXH4BJ must be in thermal equilibrium with t j =25 c. 3. the surge may be repeated after the TISP4XXXH4BJ returns to its initial conditions. 4. see applications information and figure 11 for current ratings at other temperatures. 5. eia/jesd51-2 environment and eia/jesd51-3 pcb with standard footprint dimensions connected with 5 a rated printed wiring track widths. see figure 8 for the current ratings at other durations. derate current values at -0.61 %/ c fo r ambient temperatures above 25 c. absolute maximum ratings, t a = 25 c (unless otherwise noted) description this TISP4XXXH4BJ range consists of six voltage variants to meet various maximum system voltage levels (135 v to 275 v). they a re guaran- teed to voltage limit and withstand the listed international lightning surges in both polarities. these high (h) current protec tion devices are in a plastic package smbj (jedec do-214aa with j-bend leads) and supplied in embossed carrier reel pack. for alternative voltage and holding current values, consult the factory. for lower rated impulse currents in the smb package, the 50 a 10/1000 tisp4xxxm3bj series is available.
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series thermal characteristics electrical characteristics, t a = 25 c (unless otherwise noted) pa rameter test conditions min. typ. max. unit i drm repetitive peak off- st ate current v d = v drm t a = 25 c t a = 85 c 5 10 a v (bo) breakove r voltage dv/dt = 750 v/ms, r source = 300 ? 4165 4180 4200 4265 4300 4350 165 180 200 265 300 350 v v (bo) impuls e breakover voltage dv/dt 1000 v/ s, linear voltage ramp, maximum ramp value = 500 v di/dt = 20 a/ s, linear current ramp, maximum ramp value = 10 a 4165 4180 4200 4265 4300 4350 174 189 210 276 311 363 v i (bo) br ea ko ver current dv/dt = 750 v/ms, r source = 300 ? 0.15 0.8 a v t on-state voltage i t = 5a, t w = 100 s 3v i h holding current i t = 5a , di /dt = -/+30 ma/ms 0.225 0.8 a dv/dt cr itical rate of rise of o ff-state vol tage linear voltage ramp, maximum ramp value < 0.85v drm 5kv/ s i d off-state current v d = 50 v t a = 85 c 10 a c off off-state capacitance f= 100 khz, v d =1v rms, v d =0, f= 100 khz, v d =1v rms, v d =-1v f= 100 khz, v d =1v rms, v d =-2v f= 100 khz, v d =1v rms, v d =-50v f= 100 khz, v d =1v rms, v d =- 100 v (see note 6) 4165 thru ?200 4265 thru ?350 4165 thru ?200 4265 thru ?350 4165 thru ?200 4265 thru ?350 4165 thru ?200 4265 thru ?350 4165 thru ?200 4265 thru ?350 80 70 71 60 65 55 30 24 28 22 90 84 79 67 74 62 35 28 33 26 pf note 6: to avoid possible voltage clipping, the 4125 is tested with v d =-98v. pa rameter test conditions min. typ. max. unit r ja j unction to free air thermal resistance eia/jesd51-3 pcb, i t = i tsm(10 00) , t a = 25 c, (see note 7) 113 c/w 265 mm x 210 mm populated line card, 4-layer pcb, i t = i tsm(1000) , t a = 25 c 50 note 7: eia/jesd51-2 environment and pcb has standard footprint dimensions connected with 5 a rated printed wiring track widths.
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series parameter measurement information figure 1. voltage-current characteristic for t and r terminals all measurements are referenced to the r terminal -v v drm i drm v d i h i t v t i tsm i tsp v (bo) i (bo) i d quadrant i switching char acteristic +v +i v (bo) i (bo) v d i d i h i t v t i tsm i tsp -i quadra nt iii switching char acteristic pmxxaab v drm i drm
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series t ypical characteristics figure 4. figure 5. figure 2. figure 3. t j - junction temperature - c -25 0 25 50 75 100 125 150 |i d | - off-state current - a 0001 001 01 1 10 100 t chag v d = 50 v t j - junction temperature - c -25 0 25 50 75 100 125 150 normalized breakover voltage 0.95 1.00 1.05 1.10 tc4haf tc4hak v - on-state voltage - v 0.7 1.5 2 3 4 5 7 10 1 i t - on-state current - a 1.5 2 3 4 5 7 15 20 30 40 50 70 150 200 1 10 100 t a = 25 c t w = 100 s tc4haha '4265 t hru '4350 '4165 t hru '4200 t j - junction temperature - c -25 0 25 50 75 100 125 150 normalized holding current 0.4 0.5 0.6 0.7 0.8 0.9 1.5 2.0 1.0 off-state current vs junction temperature on-state current vs on-state voltage normalized breakdown voltage vs junction temperature normalized holding current vs junction temperature
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series t ypical characteristics figure 6. figure 7. v d - off-state voltage - v 0.5 1 2 3 5 10 2 030 50 1 00150 capacitance normalized to v d = 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t j = 25 c v d = 1 vrms tc4haia ' 4165 thru '4200 ' 4265 thru '4350 v drm - repetitive peak off-state voltage - v 130 150 170 200 230 270 300 c - differential off-state capacitance - pf 31 32 33 34 36 30 35 ? c = c o ff(-2 v) - c o ff(-50 v) t chaja '4165 '4180 '4200 '4300 '4350 '4265 normalized capacitance vs off-state voltage differential off-state capacitance vs rated repetitive peak off-state voltage
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series t ypical characteristics figure 8. figure 9. figure 10. figure 11. t - current duration - s 01 1 10 100 1000 i tsm (t) - non-repetitive peak on-state current - a 1.5 2 3 4 5 6 7 8 9 15 20 30 10 ti4hac v gen = 600 vrms, 50/60 hz r gen = 1.4*v gen /i tsm(t) eia/jesd51-2 environment eia/jesd51-3 pcb t a = 25 c t - power duration - s 01 1 10 100 1000 z ja (t) - transient thermal impedance - c/w 1.5 2 3 4 5 7 15 20 30 40 50 70 150 1 10 100 ti4hae i tsm (t) applied for time t eia/jesd51-2 environment eia/jesd51-3 pcb t a = 25 c t amin - minimum ambient temperature - c -35 -25 -15 -5 5 15 25 -40 -30 -20 -10 0 10 20 derating factor 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 ti4hafa '4265 thru '4350 '4165 thru '4200 t a - ambient temperature - c -40 -30 -20 -10 0 10 2 0304050607080 impulse current - a 90 100 120 150 200 250 300 400 500 600 700 iec 1. 2/50, 8/20 itu-t 10/700 fcc 10/560 bellcore 2/10 bellcore 10/1000 fcc 10/160 tc4haa non-repetitive peak on-state current vs current duration thermal impedance vs power duration v drm derating factor vs minimum ambient temperature impulse rating vs ambient temperature
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series deployment applications information impulse testing standard peak voltage setting v volt age waveform s peak current value a current waveform s tisp4xxxh4 25 c rating a series resistance ? gr -1089-core 2500 2/10 500 2/10 500 0 1000 10/1000 100 10/1000 100 fcc part 68 (march 1998) 1500 10/160 200 10/160 250 0 800 10/560 100 10/560 160 0 1500 9/720 ? 37.5 5/320 ? 200 0 1000 9/720 ? 25 5/320 ? 200 0 i3124 1500 0.5/700 37.5 0.2/310 200 0 itu-t k.20/k.21 1500 4000 10/700 37.5 100 5/310 200 0 ? fcc part 68 terminology for the waveforms produced by the itu-t recommendation k.21 10/700 impulse generator these devices are two terminal overvoltage protectors. they may be used either singly to limit the voltage between two conducto rs (figure 12) or in multiples to limit the voltage at several points in a circuit (figure 13). in figure 12, protector th1 limits the maximum voltage between the two conductors to v (bo) . this configuration is normally used to protect circuits without a ground reference, such as modems. in figure 13, protectors th2 and th3 limit the maximum voltage between eac h conduc- tor and ground to the v (bo) of the individual protector. protector th1 limits the maximum voltage between the two conductors to its v (bo) value. if the equipment being protected has all its vulnerable components connected between the conductors and ground, then pro tector th1 is not required. if the impulse generator current exceeds the protectors current rating, then a series resistance can be used to reduce the cur r ent to the protectors rated value to prevent possible failure. the required value of series resistance for a given waveform is given by t he following calculations. first, the minimum total circuit impedance is found by dividing the impulse generators peak voltage by the prote ctors rated current. the impulse generators fictive impedance (generators peak voltage divided by peak short circuit current) is then sub tracted from the minimum total circuit impedance to give the required value of series resistance. in some cases, the equipment will require veri fication over a temperature range. by using the rated waveform values from figure 11, the appropriate series resistor value can be calculated f or ambient temperatures in the range of -40 c to 85 c. to verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various imp ulse wave forms. the table below shows some common values. figure 12. two point protection figure 13. multi-point protection th1 th3 th2 th1
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. to standardize thermal measurements, the eia (electronic industries alliance) has created the jesd51 standard. part 2 of the st andard (jesd51-2, 1995) describes the test environment. this is a 0.0283 m 3 (1 ft 3 ) cube which contains the test pcb (printed circuit board) horizontally mounted at the center. part 3 of the standard (jesd51-3, 1996) defines two test pcbs for surface mount components; one for packages smaller than 27 mm on a side and the other for packages up to 48 mm. the smbj measurements used the smaller 76.2 mm x 114.3 mm (3.0 ?x 4.5 ? pcb. the jesd51-3 pcbs are designed to have low effective thermal conductivity (high thermal resistance) and represent a worse case condition. the pcbs used in the majority of applications will achieve lower values of thermal resistance and so can dissipate higher power levels than indicated by the jesd51 values. TISP4XXXH4BJ overvoltage protector series capacitance normal system voltage levels jesd51 thermal measurement method ac power testing the protector can withstand currents applied for times not exceeding those shown in figure 8. currents that exceed these times must be terminated or reduced to avoid protector failure. fuses, ptc (positive temperature coefficient) resistors and fusible resistors are overcurrent protection devices which can be used to reduce the current flow. protective fuses may range from a few hundred milliamperes to one ampere. in some cases, it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. the current versus time characteristic of the overcurrent protector must be below the line shown in figure 8. in some cases, there may be a furthe r time limit imposed by the test standard (e.g. ul 1459 wiring simulator failure). applications information the protector characteristic off-state capacitance values are given for d.c. bias voltage, v d , values of 0, -1 v, -2 v and -50 v. where possible, values are also given for -100 v. values for other voltages may be calculated by multiplying the v d = 0 capacitance value by the factor given in figure 6. up to 10 mhz, the capacitance is essentially independent of frequency. above 10 mhz, the effective capacitance is str ongly dependent on connection inductance. in many applications, such as figure 15 and figure 17, the typical conductor bias voltages will be about -2 v and -50 v. figure 7 shows the differential (line unbalance) capacitance caused by biasing one protector at -2 v and the ot her at -50 v. the protector should not clip or limit the voltages that occur in normal system operation. for unusual conditions, such as ring ing without the line connected, some degree of clipping is permissible. under this condition, about 10 v of clipping is normally possible witho ut activating the ring trip circuit. figure 10 allows the calculation of the protector v drm value at temperatures below 25 c. the calculated value should not be less than the maximum normal system voltages. the tisp4265h4bj, with a v drm of 200 v, can be used for the protection of ring generators producing 100 v r.m.s. of ring on a battery voltage of -58 v (th2 and th3 in figure 17). the peak ring voltage will be 58 + 1.414*100 = 199.4 v. however, this is the open circuit voltage and the connection of the line and its equipment will reduce the peak volt age. in the extreme case of an unconnected line, clipping the peak voltage to 190 v should not activate the ring trip. this level of clippi ng would occur at the temperature when the v drm has reduced to 190/200 = 0.95 of its 25 c value. figure 10 shows that this condition will occur at an ambient temperature of -22 c. in this example, the tisp4265h4bj will allow normal equipment operation provided that the minimum expected ambient temperature does not fall below -22 c.
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series t ypical circuits applications information fi gure 14. modem inter-wire protection figure 15. protection module fi gure 16. isdn protection figure 17. line card ring/test protection fuse tisp4350h4 ai6xbpa ring detector hook switch d.c. sink si gnal modem ring tip r1a r1b ring wire tip wire th3 th2 th1 protected equipment e. g. line card ai6xbk r1a r1b th3 th2 th1 ai6xbl si gnal d.c. test relay ring relay slic relay test equip- ment ring generator s1a s1b r1a r1b ring wire tip wire th3 th2 th1 th4 th5 slic slic protection ring/test protection o ver- current protection s2a s2b s3a s3b v bat c1 220 nf ai6xbj tisp6x xxx, tisppblx, 1/2tisp6ntp2
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series recommended printed wiring footprint device symbolization code mechanical data smb pad size mdxx bi 2.54 (.100) 2.40 (.094) 2.16 (.085) metric (inches) dimensions are: device symbolization code tisp4165h4bj 4165h4 tisp4180h4bj 4180h4 tisp4200h4bj 4200h4 tisp4265h4bj 4265h4 tisp4300h4bj 4300h4 tisp4350h4bj 4350h4 devices will be coded as below. as the device parameters are symmetrical, terminal 1 is not identified. devices are shipped in one of the carriers below. unless a specific method of shipment is specified by the customer, devices wi ll be shipped in the most practical carrier. for production quantities, the carrier will be embossed tape reel pack. evaluation quantities may b e shipped in bulk pack or embossed tape. carrier information ca rrier embossed tape reel pack TISP4XXXH4BJr bulk pa ck ti sp4xxxh4bj ti sp4xxxh4bjr-s TISP4XXXH4BJ-s for standard te rmination finish order as for lead free te rmination finish order as
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protection series smbj (do-214aa) mechanical data smb mdx xbha 2 index mark (if needed) metric (inches) dimensions are: 4.06 - 4.57 (.160 - .180) 3.30 - 3.94 (.130 - .155) 1.96 - 2.32 (.077 - .091) 0.10 - 0.20 (.004 - .008) 0.76 - 1.52 (.030 - .060) 2.00 - 2.40 (.079 - .094) 1.90 - 2.10 (.075 - .083) 5.21 - 5.59 (.205 - .220) this surface mount package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. the compou nd will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated i n high humidity conditions. leads require no additional cleaning or processing when used in soldered assembly.
november 1997 - revised february 2005 specifications are subject to change without notice. customers should verify actual device performance in their specific applications. TISP4XXXH4BJ overvoltage protector series t ape dimensions mechanical data smb package single-sprocket tape direction of feed embossment carrier tape cover tape notes: a. the clearance between the component and the cavity must be within 0.05 mm (.002 in.) (.026 in.) min. to 0.65 mm max. so that the compon n et cann ot rota te more than 20 w ithin the determined cavity. b. ta ped devices are supplied on a reel of the following dimensions:- reel diameter: 330 3.0 mm (2.95 in.) (.512 .020 in.) (12.99 .118 in.) reel hub diameter 75 mm min. reel axial hole: 13.0 0.5 mm c. 30 00 devices are on a reel. md xxbj 20 typical component cavity cent r e li ne maximium com ponent rotation typical component cent r e line index mark 3.90 - 4.10 (.154 - .161) 1.95 - 2.05 (.077 - .081) 1.55 - 1.65 (.061 - .065) 1.65 - 1.85 (.065 - .073) 5.54 - 5.55 (.215 - .219) 11.70 - 12.30 (.461 - .484) 7.90 - 8.10 (.311 - .319) 8.20 (.323) max. 0.40 (.016) max. 4.50 (.177) max. 0 min. 1.50 (.059) min. metric (inches) dimensions are: ?isp?is a trademark of bourns, ltd., a bourns company, and is registered in u.s. patent and trademark office. ?ourns?is a registered trademark of bourns, inc. in the u.s. and other countries.

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